Power amplifier and method for power amplification

ABSTRACT

The invention provides a method for reducing power dissipation in a power amplifier used in wireless communication systems, said power amplifier having transistors showing a quiescent current, wherein the quiescent current of the power amplifier is adaptively changed according to the average output power of the power amplifier. A power amplifier for use in wireless communication systems is provided, said power amplifier having transistors showing a quiescent current, comprises adaptive biasing means changing the quiescent current of the power amplifier in accordance with the average output power of the power amplifier for reducing power dissipation in the power amplifier. A UMTS hand set comprises a power amplifier as specified above.

The invention relates to a power amplifier and a method for poweramplification in modem wireless and telecommunication systems.

Modem wireless and telecommunication systems require the power amplifierto operate in linear mode to maximize the spectral efficiency of thesystem. However, linearity requirements conflict with efficiencyrequirements. Typically a linear power amplifier will be biased inclass-B or class-AB and in order to reach the linearity specificationwill be backed off from its peak envelope power PEP of about 10 dB. As aconsequence, the power added efficiency PAE of the power amplifier willbe compromised.

In power amplifiers for mobile communication the output power P_(out) isvarying according to the communication requirements. The supply voltage,which is conventionally derived from a battery, is fixed to a certainvalue. The supply current I_(DC) will vary with the output power foramplifiers that are working in class-AB or B. The output current i_(o)of a class-AB or class-B is a truncated sinusoidal current. For aclass-B, the conduction angle, i.e. the fraction of the sinusoid inwhich the power amplifier generates current, is exactly equal to π,which means also I_(Q)=0. For a class-AB the conduction angle is greaterthan π and therefore I_(Q)>0. The supply current I_(DC) is alwaysgreater than or equal to the quiescent current I_(Q).

In conventional solutions V_(DC) is set to the maximum value allowed bythe manufacturing technology, and it is provided via a supply generator(battery). The maximum power added efficiency PAE is reached at maximumoutput power. It can be shown that a power amplifier will show a poweradded efficiency lower than its maximum PAE that can be achieved whenfunctioning at Output Power levels below the maximum levels.

In state-of-the-art mobile and wireless communication schemes theaverage output power of the power amplifier is set by the network inorder to maximize the cell capacity. As a consequence, power amplifiersare not required to transmit continuously at maximum output power, butthey are very often backed off to lower power levels (in(W-)CDMA systemsusually 10 dB lower). The power amplifier will show a lower power addedefficiency and therefore a relatively higher power consumption. Forexample, it is calculated that a power amplifier for a UMTS handset withpower added efficiency PAE_(max %)=35% will show typically power addedefficiency PAE=12% at 10 dB back-off.

The power amplifier output power is varied in order to adapt it to thecommunication requirement. In (W-)CDMA systems, for instance, the outputpower is varied in order to maximize cell-capacity. The base stationmeasures the received output power from the handset and sends commandsto the handset to adjust the output power to a better value. This iscalled Power Control Loop, and an example of it can be found, for UMTSin ETSI: “UMTS TETRA standard”, chapter TS 125.101, pages 11–13, ETSI2001 and ETSI: “UMTS TETRA standard”, chapter TS 125.214, pages 10–20,ETSI, 2001.

As the output power is varied so will the supply current I_(DC); namely,as the output power is decreased, so will the supply current. In fact,the conduction angle will increase and the current I_(DC) will tend toits minimum value I_(Q). The variation of I_(DC) changes the performanceof the active devices in the power amplifier, and leads to gain andlinearity variation. At very low output power, the power dissipationwill be independent of the output power level. In this situation thepower stage is working as a class-A amplifier.

The high power dissipation of the power amplifier in modern mobile andwireless communication is affecting the performance of the communicationequipment, especially mobile equipment such as mobile telephones andterminals. This dissipation has to be reduced.

In mobile communication and wireless systems the power amplifier istypically biased in class-AB. Class-B amplifiers are affected bycross-over problems and are not linear enough to comply with thelinearity specification of communication standards. Class-A amplifiersare linear enough for the application but they dissipate far more thanclass-AB and are therefore not used. All the other classes of amplifiersare not linear enough for the standard, and require the adoption ofcomplex linearization techniques. Those techniques are not attractivefor mobile equipment implementation.

The typical power amplifier for this kind of application is divided intoa driver stage and a power stage. The driver stage could be composed ofseveral cascaded stages. The two stages are connected via a matchingnetwork between them and via two other matching networks to the inputand the output. A Biasing block sets the quiescent current of both thedriver and the power stage.

The power stage of the power amplifier is optimized for functioning atmaximum output power, in which I_(DC)>I_(Q). The linearity of thecomplete power amplifier is set to the minimum required by thespecification, in order to get the maximum achievable power addedefficiency. When working at lower output power, I_(DC) decreases in thepower stage. Because of this the gain, the input and the outputimpedance of the stage vary. These variations are usually partlycompensated for by correctly choosing the biasing of the driver stagesuch that the gain remains as constant as possible. In fact, as soon asthe power stage will start to increase (expand) its gain, because ofincreasing I_(DC), the driver stage will typically decrease (compress)the gain, so that gain flatness is achieved for a wide range of outputpower. Moreover, linearity of the power amplifier increases for loweroutput power up to a level far beyond the standard requirements.

FIG. 1 shows a block diagram of a conventional power amplifier. Twostages, a driver stage 2 and a power stage 4 are connected via amatching network 6 between them and via two other matching networks 8and 10 to the input and the output. A Biasing block 12 sets thequiescent current of both the driver and the power stage.

FIG. 2 shows a more detailed block diagram of the conventional poweramplifier of FIG. 1 where the same reference numbers are used for thesame items. The power amplifier, for example the power amplifier UAA3592of PHILIPS SEMICONDUCTORS, consists of the power stage 4 and the driverstage 2 interconnected by the matching network 6. The input matchingnetwork 8 converts the input impedance of the driver stage 2 to thenominal impedance. The output matching network 10 maximizes the outputpower and removes the higher order components and is connected to anantenna 14. Two current biasing networks 13, 15 are providing a bias tothe driver stage 2 and the power stage 4 respectively. A supply voltageVcc is fed to the driver stage 2 and the power stage 4 through RF chokes17, 19 respectively. The power amplifier has a 1 dB compression pointequal to −4 dBm with respect to the input power. Although a UAA3592 istaken as an example for the power amplifier, the considerations can beextended to any power amplifier operating in class AB for CDMA schemes.

Further bias circuits are to be found in the state of the art mentionedbelow.

U.S. Pat. No. 6,236,266 shows a bias circuit and bias supply method fora multistage power amplifier including heterojunction bipolartransistors for power amplifying a high frequency signal and suppressingan increase in Rx noise during low-power output operation of themultistage power amplifier. The bias circuit outputs a control signalVapc from an external control circuit to the base of only a first-stageamplifier HBT in the multistage power amplifier. To the base of thesecond and each later power amplifying stage HBT of the multistage poweramplifier, the bias circuit supplies a bias current regulated by voltagestabilizers according to the control signal Vapc. In U.S. Pat. No.6,236,266 the quiescent current of the amplifier is varied according tothe power level, this technique is, however, applied with the goal toreduce the noise in receiver unit.

The EP 0 734 118 A1 shows an active biasing circuit to provide linearoperation of an RF power amplifier. A current generator circuit providesa current to the stages of the RF power amplifier. In the final poweramplifier stage the current is applied to a bias control amplifier thatincludes a transistor connected as a diode. The transistor diode isconnected through a resistor to the emitter of a bias controltransistor, which is in turn connected to and controls the gate of atransistor power amplifier in the final power amplifier stage of the REpower amplifier with a bias current that is the highest current levelneeded for highest RE power. The transistor diode and the currentgenerator circuit are also connected to bias control transistors in theother stages of the RE power amplifier such that the other stages arelikewise controlled with the current from the current generator. In theEP 0 734 118 A1 the goal is to maintain linear operation.

It is the object of the invention to provide a power amplifier and amethod for power amplification wherein the power dissipation isdrastically reduced, in particular in the case of a class-AB poweramplifier.

This object is achieved by a method for reducing power dissipation in apower amplifier for use in wireless communication systems, said poweramplifier having transistors showing a quiescent current, wherein thequiescent current of the power amplifier is adaptively changed accordingto the average output power of the power amplifier.

In an advantageous embodiment of the method of the invention, theadaptive biasing of the power amplifier having at least two stages, isdone by changing the value of I_(Q) of at least one of the stages of thepower amplifier.

In an advantageous embodiment of the method of the invention, theadaptive biasing of the power amplifier having at least two stages, isdone by changing the value of I_(Q) of all the stages of the poweramplifier.

In an other advantageous embodiment of the method of the invention, theadaptive biasing of the power amplifier having at least two stages, isdone by changing the value of I_(Q) of the power stage of the poweramplifier.

In an advantageous embodiment of the method of the invention, theadaptive biasing of the power amplifier having at least two stages, isdone by detecting the average output power of the power amplifier in apower detector and varying the value of I_(Q) of the two stagesaccording to the detected power and a specified function of an adaptivebiasing network.

In an advantageous embodiment of the method of the invention, a voltageor current quantity proportional to the average output power is detectedas average output power of the power amplifier.

In an advantageous embodiment of the method of the invention, a voltageor current quantity proportional to the average output power is detectedin any of the stages of the power amplifier, preferably in a driverstage of the power amplifier.

In an advantageous embodiment of the method of the invention, theaverage output power is detected by applying a squaring function andaveraging a scaled copy of the collector current of the driver and/orpower stage.

In an advantageous embodiment of the method of the invention, theaveraging function is carried out directly after the squaring functionin the power detector.

In an other advantageous embodiment of the method of the invention, theaveraging function is carried out in the adaptive biasing network.

The above object is achieved by a power amplifier for use in wirelesscommunication systems, said power amplifier having transistors showing aquiescent current, comprising adaptive biasing means changing thequiescent current of the power amplifier according to the average outputpower of the power amplifier for reducing power dissipation in the poweramplifier.

In a power amplifier comprising the adaptive biasing means, thedissipation is decreased and gain control is improved compared tostate-of-the-art solutions. The invention is based on adaptivelychanging the quiescent current of the power amplifier according to theaverage output power, i.e. changing the value of I_(Q) of at least onestage of the power amplifier. The invention has the following advantageswhen compared to state-of-the-art linear power amplifiers.

-   1. Reduced power amplifier dissipation (typically 70% reduction in    dissipation).-   2. Full integration in the power amplifier—there is no need for    external components.-   3. No need for additional pins.-   4. Points 2 and 3 make the invention suitable for every handset    without introducing changes in the architecture of the handset or in    the layout of the PCB.

In a preferred embodiment of the power amplifier of the invention, theadaptive biasing means comprise a power detector detecting a quantityproportional to the output power of the power amplifier and an adaptivebiasing network.

In a preferred embodiment of the power amplifier of the invention, thepower detector is configured to provide a squaring function and anaveraging function on a quantity proportionals the output power of thepower amplifier.

In a preferred embodiment of the power amplifier of the invention, wherethe power amplifier comprises a driver stage, a current biasing networkconnected to the driver stage, an intermediate matching network, a powerstage, and a current biasing network connected to the power stage, thepower detector is connected to an input of the driver stage, and theadaptive biasing network is connected to the input of the power stage.

In a preferred embodiment of the power amplifier of the invention, theadaptive biasing network comprises a processing block connected to thepower detector, and a current biasing network connected between theprocessing block and the input of the power stage.

In an embodiment of the power amplifier of the invention, the processingblock comprises an analog-to-digital converter, a look-up tableperforming the function of changing the quiescent current of the poweramplifier according to the average output power of the power amplifier,and a digital-to-analog converter.

In a preferred embodiment of the power amplifier of the invention, theprocessing block comprises a differential analog circuit implementingthe function:P _(DC)(I _(Q))=min I _(Q)(P _(DC)) with ΔG<ΔG _(max) and spec(linearity)where ΔG is the gain variation and ΔG_(max) is the maximum gainvariation allowed by the application, and the spec (linearity) is thelinearity specification for the application.

In a preferred embodiment of the power amplifier of the invention, theprocessing block comprises an analog implementation circuit where adifference of I_(pow)=I_(sq)−I_(ref) is calculated in the current domainand averaging is performed by a capacitor connected between a nodecarrying I_(pow) and ground.

The analog implementation of the invention does not introduce steps inthe biasing of the power amplifier, and therefore gives continuity ofoperation.

In a preferred embodiment of the power amplifier of the invention, adiode stage is connected between a node carrying I_(pow) and ground.

In a preferred embodiment of the power amplifier of the invention, aresistor is connected between anode carrying I_(pow) and a mirrorcircuit provided at the output of the processing block and outputtingI_(out).

The above object is also achieved by a UMTS hand set comprising a poweramplifier configured as stated above.

These and various other advantages and features of novelty whichcharacterize the present invention are pointed out with particularity inthe claims annexed hereto and forming a part hereof. However, for abetter understanding of the invention, its advantages, and the objectobtained by its use, reference should be made to the drawings which forma further part hereof, and to the accompanying descriptive matter inwhich preferred embodiments of the present invention are illustrated anddescribed.

FIG. 1 shows a block diagram of a conventional power amplifier.

FIG. 2 shows a more detailed block diagram of the conventional poweramplifier of FIG. 1, for example the power amplifier UAA3592 of PHILIPSSEMICONDUCTORS.

FIG. 3 shows a block diagram of a power amplifier according to anembodiment of the invention.

FIG. 4 shows a more detailed block diagram of the power amplifieraccording to an embodiment of the invention as shown in FIG. 3.

FIG. 5 shows a circuit diagram of a differential implementation of thepower detector used in the power amplifier according to an embodiment ofthe invention as shown in FIG. 4.

FIG. 6 shows a block diagram of a digital implementation of the adaptivebiasing network shown in FIG. 4.

FIG. 7 shows, in the analog domain, an analog implementation of theadaptive biasing network shown in FIG. 4.

FIG. 8 shows, in the current domain, an analog implementation of theadaptive biasing network shown in FIG. 4.

FIG. 9 shows a simulated I_(Q) for the sliding biasing according to theinvention and conventional biasing for a UMTS power amplifier.

FIG. 10 shows a simulated IM3 for the sliding biasing according to theinvention and conventional biasing for a UMTS power amplifier.

FIG. 11 shows a simulated power dissipation versus output power for thesliding biasing according to the invention and conventional biasing fora UMTS power amplifier.

FIG. 3 again shows a power amplifier having the driver stage 2 and thepower stage 4 which are connected via a matching network 6 between themand via the two matching networks 8 and 10 to the input and the outputand to the antenna 14. The adaptive biasing means of the inventioncomprise a power detector 16 and an adaptive biasing circuit 18. Thepower detector 16 detects the average output power of the poweramplifier and feeds it to the adaptive biasing circuit 18. The adaptivebiasing circuit 18 varies the value of I_(Q) of the two stages 2, 4according to the detected power and a specified function. According toFIG. 3, the power detector senses the power at the output of the driverstage 2. However this sensing could be performed in any part of thepower amplifier (input of the driver stage 2, output of the driver stage2, input of the power stage 4, output of the power stage 4); what isimportant is that a quantity (voltage or current) is produced that isproportional to the average output power.

In order to avoid clipping and/or crossover effect reducing the accuracyof the power detector 16, it is advantageous to perform the powersensing in nodes in which the signals are fully sinusoidal; therefore itis recommendable to perform the sensing in the driver stage, which ismostly acting as a class-A.

FIG. 4 shows the schematic of a linear power amplifier for UMTS withadaptative biasing with sliding biasing current using the adaptivebiasing means 16, 18 driven by the input power. Basically, the RF poweris read at the input of the power amplifier. Then the RF power controlsquiescent current of the power stage 4. The adaptive biasing meanscontrolled by the RF power has been divided into three sub-logicalblocks: power detector 16, offset eraser 20 and processing block 22. Inthis embodiment, the power detector 18 is connected to the input of thedriver stage 2. The offset eraser is connected between the currentbiasing network 13 and the processing block 22. The processing block isconnected to the offset eraser 20 and to the power detector 18 and,furthermore, via the current biasing network 15 to the input of thepower stage 4. The current biasing network 15 receives a signal I_(SLID)(P_(in)) which is a sliding biasing current depending on the inputpower, and feeds the power stage 4.

The power detector 16 produces a DC current proportional to the RFpower, the offset eraser 20 cancels the DC offset of the power detector16 due to the biasing and the processing block 22 performs filtering,integration and clipping function. In order to implement slidingbiasing, it is needed to know the RF input or output power of the poweramplifier. The RF power is sensed at the input of the power stage 2(FIG. 4). This information is transformed by the power detector 16 intoa current. The following processing block 19 avails to process thiscurrent.

The best way to implement a power detector 16 is utilizing a squaringfunction and averaging on a scaled copy of the collector current of thedriver and/or power stage as shown in FIG. 5. To put the averagingfunction directly after the squaring function is possible but notneeded. Averaging could be done also in the adaptive biasing circuit.

FIG. 5 shows a more detailed circuit of the power detector 16 in thepower amplifier environment. A reference current I_(ref) is fed via asquaring circuit 26 to a transistor Q3 the base of which is connected tothe base of a transistor Q1 which is fed by I_(bias). A furthertransistor Q4 is connected between I_(bias) and via a resistor R1 to thebase of the transistor Q1. The resistor is connected via an inductance28 to a resistor R2 which is connected via a capacitance 30 a terminalcarrying RF_(in). The node between the resistor R2 and the capacitance30 is connected to the base of a transistor Q0. The collector of thetransistor Q0 is connected to a terminal carrying RF_(out). The base ofthe transistor Q0 is connected to the base of a transistor Q2, thecollector of which transistor is connected to a further squaring circuit32 which outputs I_(sq)

FIG. 5 shows the strategy to sense the RF and quiescent current. The RFcurrent is sensed directly on the base of the driver BJT(Q0). In orderto compensate for the offset created by the I_(DC) of the driver stage,the quiescent level is detected on the biasing network by Q3.Duplicating the circuit of the power detector 16 to implement the offseteraser 20 permits to compensate for the temperature variations. As thisoffset eraser 20 is fed only with the quiescent component portion of thedriver BJT, it compensates for the offset created by Ic_(Q1−Q). Thebipolar Q2 senses the RF signal, while Q3 detects only the portion ofthe quiescent current. Actually the inductor interrupts the RF path andconsequently it ensures a decoupling between bias and RF circuits. Theoffset compensation can be performed by means of an independent currentreference. This solution seems to be easier to implement, but thetemperature changes in the power amplifier and tolerance introduced bythe power detector will not be compensated for. To adopt a copy of powerdetector permits partially to compensate for these variations.

In order to counteract temperature variations and DC-offset adifferential approach can be used in the power detector. FIG. 5 showsthe differential implementation of the power detector. The RF powertransistor is transistor Q0. The current I_(bias) is mirrored by thetransistor pair Q1−Q0 to transistor Q0. The quiescent current oftransistor Q0 will be equal to:I _(Q,0) =I _(bias) ×A ₀ /A ₁ =m×I _(bias),  (1)

where A₀ and A₁ are the emitter area of transistor Q0 and transistor Q1respectively. The collector current of transistor Q0 is mirrored totransistor Q2. Transistor Q2 is chosen to be smaller than transistor Q0.In order to reduce power dissipation, transistor Q2 senses the currentof transistor Q0 according to the equation:I _(c2) =I _(c0) ×A ₂ /A ₀=1/n×I _(c0),  (2)

where I_(c0) and I_(c2) are the collector currents of transistor Q0 andtransistor Q2, respectively, and n is the ratio between the emitterareas of transistor Q2 and transistor Q0. Because of this the quiescentcurrent of transistor Q2 will be proportional to the quiescent currentof transistor Q0, transistor Q3 does not receive an RF signal on itsbase, because of the filtering effect of the inductance; therefore itscollector current is constant and proportional to I_(bias). If theemitter area ratio transistor Q3 to transistor Q1 is properly chosen,then the collector current of transistor Q3 will be equal to thequiescent current of transistor Q2. Therefore:I _(C3) =A ₃ /A ₁ ×I _(bias) =A ₃ /A ₁ ×n/m×I _(Q,2)  (3)If A ₃ /A ₂ =n/m=A ₂ /A ₁ than I _(C3) =I _(Q,2)  (4)

The additional sensing transistor Q3 is used to compensate fortemperature and biasing effects and cancel the I_(Q)-term from theoutput.

The collector currents of transistor Q1 and transistor Q3 will besquared, averaged and subtracted or, alternatively, squared, subtractedand averaged resulting in I_(SQ). SubtractingI _(SQ) =I ² _(C2)=1/n ²×(I ² _(Q) +I ² ₀/2−I ² ₀/2 cos (4πft))  (5)fromI _(ref) =I ² _(C1) =I ² _(Q) /n ²  (6)

While neglecting the high-frequency terms one gets an output current:I _(pow) =I _(SQ) −I _(ref) =I ² ₀/2n ²  (7)

I_(pow) is directly proportional to the square amplitude of the currentof the amplified signal and therefore to the average power. Since thequiescent current term does not appear in equation 7, the slidingbiasing technique can be applied also to the same transistor on whichthe sensing is performed; in fact, what is controlled (the quiescentcurrent) is not present in the sensed quantity (power indicatorI_(pow)). In this way there is no risk of oscillation, which will bepresent in the case where the controlled quantity I_(Q) will be presentalso in the sensed quantity.

In equation 5 it is assumed that the sensed amplifier works in class-A,i.e. that the sensed current has a perfect sinusoidal shape. Even thoughthis assumption is not general, in order to reduce distortion effectsand dissipation sensing is likely to occur at the output of the driverstage, which is mostly a class-A. Moreover, if the driver stage is aclass-AB, the power sensing is likely to be needed only in a limitedrange of output power (and surely in back-off from the maximum power),which is expressed in equations 9a–9c by the parameters P₁ and P₂. Inthis condition the driver stage is likely to work in class-A or veryclose to class-A, so that equation 5 represents an appropriateapproximation.

In equations 5 and 6 it is assumed that the squaring function isperfect. This is not necessary, and squaring circuits having lowaccuracy can be used as well. In fact, the high-frequency tones will beeliminated by the averaging and the effect of the quiescent current willbe eliminated by the cancellation. Ultimately, the important thing is tohave a monotone (Bi-univocal) function of the output power.

The goal of the adaptive biasing circuit is to generate an optimal I_(Q)for the power amplifier with respect to the average output power.Therefore this block must function such that the dissipated power is atminimum with the linearity and gain variation constraint imposed, thatis:P _(DC)(I _(Q))=min I _(Q)(P _(DC))  (8)

With ΔG<ΔG_(max) and spec (linearity) where ΔG is the gain variation andΔG_(max) is the maximum gain variation allowed by the application, andthe spec (linearity) is the linearity specification for the application.This specification is usually in terms of ACLR and/or EVM but could beany linearity specification. In case of ACLR specification it could beuseful to translate it into IM3 specification. The chosen functiontherefore depends on the type of power amplifier and on the applicationchosen.

The choice of the optimal adaptive I_(Q) is strongly dependent on theapplication constraints. At very low power a conventional linear poweramplifier is far more linear than required from the specifications. Inthis operating region the power amplifier acts as a class-A, and its IM3(3^(rd) order inter-modulation product) will be very low. The IM3 isdictating the linearity performance of linear power amplifiers. The IM3,for a linear power amplifier, decreases with 2 dB/dB slope withdecreasing power, when backing off far from the 1 dB compression point.

One could think of decreasing I_(Q) up to a value reaching the minimumIM3 allowed from the standard. However, at very low power, variation onthe gain is important. Decreasing I_(Q) from its optimal value to alower value, can also bring about gain variation. In WCDMA standards(like UMTS), the gain variation should always be kept below a certainvalue, typically ΔG_(max)=1 dB. This represents the main constraint inthe choice of the function I_(Q)=I_(Q)(P_(out)) at low P_(out).

The consequences for power dissipation when a lower I_(Q) is chosen, arethat the DC collector current I_(DC) starts to increase for output powerhigher than 0 dBm. However, in low-quiescent current operation, therelative variation is much stronger. For the lower I_(Q) values a gainvariation is observed around P_(out)=0 dBm. For an output power higherthan 20 dBm, I_(DC) is not strongly influenced by the choice of I_(Q).

I_(Q)=I_(Q)(P_(out)) is chosen as follows:

-   a) for low power: choose I_(Q) as the minimum current allowing a    gain variation smaller than the maximum allowed,-   b) for intermediate power: vary I_(Q) such that the linearity    constraint is respected (typically IM3),-   c) for high power: choose I_(Q) to the nominal value, since it will    not affect the dissipation.

The implementation of this function could be done in the digital domainvia an analog-to-digital converter ADC, a look-up table LUT and adigital-to-analog converter DAC as illustrated in FIG. 6. Theanalog-to-digital converter ADC digitizes the output of the powerdetector and passes it onto a look-up table which computes the correctvalue of quiescent current. This value will be passed onto thedigital-to-analog converter DAC to be converted into the actual I_(Q)(or a scaled version of it) to be fed to the biasing networks.

In the analog implementation of the adaptive biasing circuit, an analogblock has to implement the function I_(Q)=I_(Q)(P_(out)) as in formula10. The quantity P_(out) is fed to the circuit via a voltage or acurrent generated by the power detector. The analog implementation is tobe preferred to the digital implementation because, in the digitalimplementation, quantization noise on the quiescent current couldintroduce disturbances in the RF signal.

A possible implementation of the function could be expressed as follows:

$\begin{matrix}\begin{matrix}{I_{Q} =} & I_{Q1} & {\mspace{340mu}{P_{out} \leq P_{1}}}\end{matrix} & \left( {9a} \right) \\\begin{matrix}{I_{Q} =} & \frac{\left. {{\left( {I_{Q2} - I_{Q1}} \right)P_{out}} + {{II}_{Q1}P_{2}} - {{II}_{Q2}P_{1}}} \right)}{P_{2} - P_{1}} & {{{for}\mspace{14mu} P_{1}} \leq P_{out} \leq P_{2}}\end{matrix} & \left( {9b} \right) \\\begin{matrix}{I_{Q} =} & I_{Q2} & {\mspace{340mu}{P_{out} > {Ps}}}\end{matrix} & \left( {9c} \right)\end{matrix}$

These equations state that for output power lower than a level Pr thequiescent current should be set to the value I_(Q1). For output powerlarger than P₂ then the quiescent current should be set to I_(Q2). Forintermediate values the quiescent current should be set to intermediatevalues. The function expressed in equations 9a–9c has the advantage ofbeing extremely simple and of easy implementation. It should be notedthat, most presumably, for lower output power the quiescent current canbe kept small. Therefore I_(Q1)<I_(Q2). One can conclude that the savedpower, at low output power levels, is given by the quantity:P _(saved) =V _(DC)(I _(Q2) −I _(Q1))  (10)

An implementation in the analog domain is represented in FIG. 7. Theresistors R2,1 and RR2,2 and the capacitors C1 and C2 implement theaveraging function, removing the high-frequency content of the currentI_(sq) and I_(ref) (since I_(ref) should not have high-frequency contentthe capacitor on its branch could be removed). Resistors R2,1 and R2,2convert the low-frequency content of the currents I_(sq) and I_(ref)into a voltage V=R₂(I_(sq)−I_(ref)). This voltage is then reconverted toa current by the differential power amplifier. The biasing currentI_(bias) is fed via two resistors R1,1 and R1,2 to the emitters oftransistors T1 and T2 which are connected to the node between thecapacitor C1 and the resistor R2,1 and the node between the capacitor C2and the resistor R2,2 respectively. The collectors of the transistors T1and T2 are carrying I_(out+) and I_(out−) respectively. I_(sq) is outputfrom R2,1 and I_(ref) is fed to R2,2.I _(out) =I _(out+) −I _(out−) =R2/2 R1(I _(sq) −I _(ref))  (11)

Equation 11 holds up to the output current not larger than the biasingcurrent of the differential power amplifier, that is I_(out)≦I_(B).

The behavior of this circuit can be analyzed with respect to equations9a–9c as follows. At very low power the RF signal will not be able togenerate an additional DC current in the transistor Q2 in FIG. 5.Therefore:Ic2=Ic3I_(sq)=I_(ref)I_(out)=0.  (12)At intermediate power:I _(c2) >I _(c3) I _(sq) −I _(ref) =I _(pow)>0I _(out) =R2/2R1×I_(pow)  (13)At very high power the differential pair will saturate, andI_(out)=I_(B).  (14)

The equations 11–14, unless an additional constant, perfectly implementequationV_(DC)=V_(max).  (15)

An implementation of the processing block 22 in the current domain ofthe adaptive biasing circuit is represented in FIG. 8. The differenceI_(pow)=I_(sq)−I_(ref) is formed in the current domain, beforeaveraging, which is performed by the capacitor C connected between nodeA (V1) and ground. The output current is equal to the low-poweramplifier filtered version of I_(pow), as desired. The clipping at highlevels is performed by the resistor R and three diodes D1 to D3connected between node A (V1) and ground. In fact the maximum outputcurrent is reached when the voltage at the node A is maximum, i.e.V_(A)=3V_(D). In this case the current flowing through the resistor Rwill be equal to I_(R)=(3V_(D)−V_(B))/R, V_(B) being the voltage at theinput of the current mirror, which may be assumed to be constant.

The circuit of FIG. 8 has two inputs I_(sq) and I_(ret) and one outputI_(out). I_(sq) comes from the power detector. The input I_(ret) comesfrom the reference circuit and it avails to erase the offset containedin I_(sq). The diodes D1 to D3 are to clip the current as the nominalcurrent level is reached. Above a certain output power, V₁ is largeenough to permit the diodes to conduct. So the saturation of the outputcurrent I_(out). starts, and excess I_(det) flows through the diodes D1to D3. The I_(RF) contained in I_(sq) is removed by the capacitor C. Thecapacitor C carries out two functions: filtering of the RF signal andwith the resistor R integrating the DC current related to the RF power.So only I_(det) is able to pass through resistor R and is then mirroredby the current mirror 40 in the output branch. As the power RFincreases, I_(det) increases as well. Consequently, also V₁ at node Aincreases and V₂ at node B remains constant.

In FIG. 9 the simulated I_(Q) as implemented by the circuit representedin FIG. 8 is represented. This implementation allows a gain variationsmaller than 1 dB (ΔG<ΔG_(max)=1 dB). The consequences for linearity areshown in FIG. 10. It is possible to notice that, even if the IM3 islarger than the one in the conventional solution, we are still far belowthe required IM3. In order to estimate the reduction in powerdissipation due to the technique, P_(out) probability distributions ofthe (W-)CDMA schemes should be taken into account as explained in [6].With the power probability distribution taken into account, this methodcauses a reduction in power consumption of up to 70%.

FIG. 9 shows the quiescent current in the power stage in mA versus theoutput power in dBm in case of conventional biasing and sliding biasing.Since the quiescent current determines the dissipation in back-offcondition and for a large portion of the time the power amplifier willoperate in this region, FIG. 9 implicitly shows a drastic reduction ofthe power dissipation. The quiescent current actually has been decreasedby 3.5 times.

FIG. 10 shows IM3 in dBc versus the output power dBm in case ofconventional and sliding biasing. With the choice of the minimumquiescent current starting from very low RF power, the course of the IM3curve will be parallel to the IM3 curve of the conventional poweramplifier, but will stay above it. It is worth noting that the slidingbiasing acts so that the linearity specification of the UMTS standard isfulfilled.

Both curves have been obtained by supplying the power stage with thequiescent currents. The sliding current has been chosen so that the IM3curve of the sliding power amplifier is below the IM3 threshold for UMTSrequirements in back-off condition. As the RF power is increased IM3exceeds the −40 dBc threshold. In this region the current is increasedto recover the linearity and overcome the failure to meet thespecification. Over the range between 0 dBm and 15 dBm there is acompensation between gain flatness and signal level, this is why theΔIM3 remains almost constant.

In the range beyond 20 dBm the conventional level of quiescent currentof the power stage is restored. In fact in this sector the DC current ofthe power stage does not depend on the quiescent current anymore,providing no advantage in the holding of a low bias point in terms ofpower saving. Then the IM3 curve of the sliding power amplifier overlapsthe conventional power amplifier curve and the power amplifier will beable to deliver the maximum power with the necessary linearity. Slidingbiasing has been carried out according to the biasing curve describedwith reference to FIG. 9.

FIG. 11 shows the power dissipation in mW versus output power in dBm inthe case of sliding and conventional biasing for the UAA3592 poweramplifier. The DC power dissipation has been reduced up to one third indeep back-off, i.e. the sliding biasing impact on the power consumption.The phone power distribution can be interpreted as a weighting functionof the DC power dissipation shown in FIG. 11. Since the power amplifierspends 80% of the time for Pout<15 dB, and the DC power consumption inthis region being strongly reduced as the quiescent current isdecreased, this means that the sliding biasing technique is suitable toimprove the consumption performance of the power amplifier. Furthermore,it has been verified that additional circuitry for the sliding biasingdissipates less than 1 mW. Hence it does not spoil the power saving ofthe power amplifier.

The proposed invention, with the power detector in a MOS form,implemented in a differential way as described in FIG. 5 and theadaptive biasing circuit as represented in FIG. 8, is underimplementation for a UMTS power amplifier where the design is based onthe UAA3592. The simulation results show feasibility of the inventionand achieved results.

The invention can be applied to all class-A and class-AB poweramplifiers working with a range of different output powers. At thismoment an implementation is carried on for a UMTS power amplifier.However the invention can be successfully implemented for all the mobilecommunication standards (e.g. EDGE, UMTS, CDMA. W-CDMA, TD-SCDMA) andwireless standards requiring linearity of the power amplifier. Theinvention can applied to Bipolar and/or (MOS)FET power amplifiers,independent of the technology they use (Si, SiGe, GaAs, InP). Allcircuits presented in the application are in a BJT format but they caneasily implemented in a MOSFET way.

New characteristics and advantages of the invention covered by thisdocument have been set forth in the foregoing description. It will beunderstood, however, that this disclosure is, in many respects, onlyillustrative. Changes may be made in details, particularly in matters ofshape, size, and arrangement of parts, without going beyond the scope ofthe invention. The scope of the invention is, of course, defined in thelanguage in which the appended claims are expressed.

1. Method for reducing power dissipation in a power amplifier for use inwireless communication systems, said power amplifier having transistorsshowing a quiescent current, wherein the quiescent current of the poweramplifier is adaptively changed according to the average output power ofthe power amplifier.
 2. The method of claim 1, wherein the adaptivebiasing of the power amplifier having at least two stages, is done bychanging the value of I_(Q) of at least one of the stages of the poweramplifier.
 3. The method of claim 1, wherein the adaptive biasing of thepower amplifier having at least two stages, is done by changing thevalue of I_(Q) of all the stages of the power amplifier.
 4. The methodof claim 1, wherein the adaptive biasing of the power amplifier havingat least two stages, is done by changing the value of I_(Q) of the powerstage of the power amplifier.
 5. The method of claim 1, wherein theadaptive biasing of the power amplifier having at least two stages, isdone by detecting the average output power of the power amplifier in apower detector and varying the value of I_(Q) of the two stagesaccording to the detected power and a specified function of an adaptivebiasing circuit.
 6. The method of claim 1, wherein a voltage or currentquantity proportional to the average output power is detected as averageoutput power of the power amplifier.
 7. The method of claim 1, wherein avoltage or current quantity proportional to the average output power isdetected in any of the stages of the power amplifier, preferably in adriver stage of the power amplifier.
 8. The method of claim 5, whereinthe average output power is detected by applying a squaring function andaveraging a scaled copy of the collector current of the driver and/orpower stage.
 9. The method of claim 8, wherein the averaging function iscarried out directly after the squaring function in the power detector.10. The method of claim 8, wherein the averaging function is carried outin the adaptive biasing circuit.
 11. A power amplifier for use inwireless communication systems, said power amplifier having transistorsshowing a quiescent current, comprising adaptive biasing means changingthe quiescent current of the power amplifier according to the averageoutput power of the power amplifier for reducing power dissipation inthe power amplifier.
 12. The power amplifier of claim 11, wherein theadaptive biasing means comprise a power detector detecting a quantityproportional the output power of the power amplifier and a adaptivebiasing circuit.
 13. The power amplifier of claim 12, wherein the powerdetector is configured to provide a squaring function and an averagingfunction on a quantity proportional to the output power of the poweramplifier.
 14. The power amplifier of claim 12, comprising a driverstage, a current biasing network connected to the driver stage, anintermediate matching network, a power stage, and a current biasingnetwork connected to the power stage, wherein the power detector isconnected to an input of the driver stage, and the adaptive biasingcircuit is connected to the input of the power stage.
 15. The poweramplifier of claim 12, wherein the adaptive biasing circuit comprises aprocessing block connected to the power detector, and a current biasingnetwork connected between the processing block and the input of thepower stage.
 16. The power amplifier of claim 15, wherein the processingblock comprises an analog-to-digital converter, a look-up tableproviding the function of changing the quiescent current of the poweramplifier according to the average output power of the power amplifier,and a digital-to-analog converter.
 17. The power amplifier of claim 15,wherein the processing block comprises a differential analog circuitimplementing the function:P _(DC)(I _(Q))=min I _(Q)(P _(DC)) with ΔG<ΔG _(max) and spec(linearity) where ΔG is the gain variation and ΔG_(max) is the maximumgain variation allowed by the application, and the spec (linearity) isthe linearity specification for the application.
 18. The power amplifierof claim 15, wherein the processing block comprises an analogimplementation circuit where a difference of I_(pow)=I_(sq)−I_(ref) iscalculated in the current domain and averaging is performed by acapacitor connected between a node carrying I_(pow) and ground.
 19. Thepower amplifier of claim 18, wherein a diode stage is connected betweena node carrying I_(pow) and ground.
 20. The power amplifier of claim 18,wherein a resistor is connected between a node carrying I_(pow) and amirror circuit provided at the output of the processing block andoutputting I_(out).
 21. A UMTS hand set comprising a power amplifierconfigured as claimed in claim 11.